Currently, deep-submicron complementary metal-oxide-semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. A ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous). The drain and source regions generally include shallow source and drain extension regions that are disposed partially underneath the gate to enhance transistor performance. The shallow source and drain extensions help to achieve immunity to short-channel effects that degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. The shallow source and drain extensions and, hence, controlling short-channel effects are particularly important as transistors become smaller.
As the size of the transistors disposed on ICs decreases, transistors with shallow ultra-shallow source drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with a junction depth of less than 30 nanometer (nm). Forming source and drain extensions with junction depth of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extensions vertically downward into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
To overcome these difficulties, source and drain regions can be raised by selective silicon epitaxy to make connections to the source and drain contacts less difficult. The raised source and drain regions provide additional material for a contact silicidation process and reduced deep source/drain junction resistance and source/drain series resistance.
Raised source/drain processes employing disposable spacers have been used, but are not suitable as dimensions decrease, such as 65 nm technology nodes and below. FIGS. 16a-16c and FIGS. 17a-17d depicts some of the concerns with these approaches.
In FIG. 16a, a gate electrode 72 is provided on a substrate 70. A silicon nitride cap 74 serves to protect polysilicon gate electrode 72 from unwanted silicon growth during the selective epitaxial growth (SEG) process. The SEG process is selective towards silicon nitride, and as a result, no silicon will be grown on top of the gate electrode 72 during the SEG process.
An oxide, such as TEOS, or LTO oxide is used to form oxide liner 76. Following the formation of the oxide liner 76, a pair of sidewall spacers 78 are formed, from silicon nitride, for example. Formation of the silicon nitride spacers 78 is typically accomplished by deposition of a silicon nitride layer, followed by dry etching.
Prior to the SEG process, a wet-etch, such as a HF wet-etch, needs to be performed to remove the oxide of the oxide liner 76. Removal of the oxide is necessary since epitaxial silicon only grows on silicon surfaces. Presence of the oxide liner 76 on the substrate 70 would prevent such growth and prevent the formation of raised source/drains.
Since the oxide liner 76 is between the nitride cap layer 74 and the nitride spacers 78, a cavity can be etched during the HF wet-etch. This cavity may reach the polysilicon gate electrode 72. Since TEOS or LTO etches rapidly in HF, the probability of exposing the top left and right corners of the polysilicon gate electrode 72 is high. As a result of this exposure of the corners of the polysilicon gate electrode 72, the formation of the raised source/drain 80 creates mouse-like ears 82 to form, as depicted in FIG. 16b. The ears 82 are highly undesirable.
Referring now to FIG. 16c, the disposable nitride spacers 78 are removed to allow halo and extension implants. However, the ears 82 effectively block the implants from being properly performed. Hence, the device becomes unusable or at least severely impaired.
Another method of forming raised source/drains avoids the use of a deposited oxide liner, but instead uses a thermally grown oxide. However, as will be readily understood, the approach is not scaleable since a thinner nitride cap does not survive a nitride spacer etch, while a thinner nitride spacer results in shadow effects for the halo ion implantation process.
Referring now to FIGS. 17a-17d, a gate electrode 92 is formed on a substrate 90. A nitride cap 94 is provided on top of the polysilicon gate electrode 92. An oxide liner 96 is thermally grown, and does not cover the silicon nitride cap 94. Disposable sidewall spacers 98 are provided on the thermally grown oxide 96.
FIG. 17b depicts the structure of FIG. 17a after the formation of the raised source/drain in an ideal process. However, the top of the cap layer 94 is partially etched in the spacer etch process, so that the cap layer 94 cannot be scaled down as much as desired. The cap layer nitride loss is related to the over etch of the spacer etch process. The result of the nitride cap loss is depicted in FIG. 17c, in which “mouse ears” 102 are formed. In this figure, the nitride spacers 98 are removed by the nitride removal etch process. The mouse ears 102 prevent the halo implantation process from satisfactorily achieved. An alternative to making the cap 94 thicker is to maintain the cap 94 thin, and making the spacers 98 narrower such that the removal of the nitride spacers does not result in an overetch that exposes the top of the polysilicon gate electrode 92 prior to the SEG process. However, as depicted in FIG. 17D, the use of thin nitride spacers results in an insufficient gap between the polysilicon gate electrode 92 and the raised source drain regions 100. The halo implants, which are typically performed with a high tilt, will not be able to be performed efficaciously due to the shadow effects caused by the raised/source drains 100. In other words, the edges of the raised source/drains are too close to the sidewalls of the polysilicon gate electrode 12.